WORKAROUND: arm64: dts: qcom: enable ethernet on the QPS615 switch for RB3Gen2, Lemans EVK, and Monaco EVK#335
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Mar 6, 2026
| bus-range = <0x5 0xff>; | ||
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| pci@0,0 { | ||
| eth0_pci: pci@0,0 { |
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Sure, will remove the label and reference pcieport* in the new .dtsi files.
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| pci@0,1 { | ||
| eth1_pci: pci@0,1 { |
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| #include <dt-bindings/interrupt-controller/irq.h> | ||
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| ð0_pci { |
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I think you use node name directly and avoid adding labelling
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| ð1_pci { |
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| #include <dt-bindings/interrupt-controller/irq.h> | ||
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| ð0_pci { |
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| pci@0,1 { | ||
| eth1_pci: pci@0,1 { |
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| ð0_pci { |
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| }; | ||
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| ð1_pci { |
| bus-range = <0x5 0xff>; | ||
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| pci@0,0 { | ||
| eth0_pci: pci@0,0 { |
| }; | ||
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| pci@0,1 { | ||
| eth1_pci: pci@0,1 { |
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Changes since the last review:
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…switch Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <[email protected]>
…15 switch Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <[email protected]>
…15 switch Enable the 10GbE and 2.5GbE ethernet ports of the QPS615 PCIE switch. Signed-off-by: Mohd Ayaan Anwar <[email protected]>
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This PR enables the 10GbE (AQR113C) and 2.5GbE (QCA8081) Ethernet ports of the QPS615 PCIe switch on three Qualcomm platforms: RB3Gen2, IQ 9075 EVK, and IQ 8275 EVK.
Each platform follows the same pattern:
eth0_pci:andeth1_pci:DT node labels to the existingpci@0,0andpci@0,1nodes insidepcie@3,0in the board's base DTS/DTSO*-qps615.dtsifile containing all QPS615-specific configuration (regulators, PHY reset GPIOs, WoL interrupt pinctrl, and IOMMU groups)Exception details: Until the QPS615 driver is upstreamed (third party ETA: end of 2026), an exception has been approved to include the driver and its devicetree entries as an out of tree DLKM only for QLI 2.0. (QLIJIRA-99, QLIJIRA-104).