From dbb261a7418fdcf9109c79759f73af5b0db65509 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 10 Oct 2024 11:24:06 +0200 Subject: [PATCH] scripts: load CLKGATE_MAP_FILE as lib and techmap it Signed-off-by: Emil J. Tywoniak --- flow/scripts/synth.tcl | 5 +++++ flow/scripts/synth_preamble.tcl | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index ec1c3445c8..6d3b34d140 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -35,6 +35,11 @@ if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} { techmap -map $::env(LATCH_MAP_FILE) } +# Technology mapping of ICGs +if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} { + techmap -map $::env(CLKGATE_MAP_FILE) +} + set dfflibmap_args "" foreach cell $::env(DONT_USE_CELLS) { lappend dfflibmap_args -dont_use $cell diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 7bbf084a67..50b2750bcd 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -48,7 +48,7 @@ if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} { # Read platform specific mapfile for OPENROAD_CLKGATE cells if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} { - read_verilog -defer $::env(CLKGATE_MAP_FILE) + read_verilog -lib $::env(CLKGATE_MAP_FILE) } # Mark modules to keep from getting removed in flattening